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Advanced Digital Design with the Verilog(TM) HDL

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Title: Advanced Digital Design with the Verilog(TM) HDL
by Michael D. Ciletti
ISBN: 0-13-089161-4
Publisher: Prentice Hall
Pub. Date: 13 August, 2002
Format: Hardcover
Volumes: 1
List Price(USD): $116.00
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Average Customer Rating: 5 (3 reviews)

Customer Reviews

Rating: 5
Summary: Excellent book for intermedate/advanced digital designers
Comment: If you want to go from designing basic building blocks to the next level: this is one of the few books out there that can do that for you. The author builds up speed quickly, but he provides complete examples(not code fragments) with simulation waveforms. Most of the code is available on his web site.

The 1st chapter is a good review of digital design(usually one half of a basic design book).His examples are excellent case studies,including architectures for arithmetic processors. There is a chapter on memories,on the structure of the different FPGAs and chapters on all stages(eg test and synthesis) of FPGA/ASIC.The author is an excellent teacher as this book shows.

(If you are struggling beginner-type student try the modeling,synthesis and rapid prototyping book first.)

Advanced digital design is an excellent book.
I recommend it for both experienced engineers and students!

Rating: 5
Summary: A good book for advanced classes on Logic design
Comment: I am using this book for my graduate level classes on "Digital System Design Automation (From HDL to FPGA)". The book is very useful - It has, from one hand a very reasonable methodology behind. From the other hand it is an excellent collection of design examples. Especially important is the fact that the book is bundled with Xilinx ISE Student edition tools. The book is fully supported by presentation slides available from the author.

Rating: 5
Summary: The most used book in my library.
Comment: Simply put, this is an excellent book. I have five books on my bookshelf covering HDL, and this book is by far the most informative and practical. The number of examples containing Verilog code, a test bench, a synthesized netlist, and simulation results is incredible. It covers some very important topics in detail that my other books don't even mention (design partitioning, clock domain synchronization, and proper gating of clocks immediately come to mind). I especially like the in-depth treatment the book gives to writing sythesizable code. Synthesis isn't an after thought; it is a primary focus exactly as it should be. The index is sufficient and larger than most books, but this book deserves more.

As an experienced engineer and engineering manager, I have used the text to provide examples, algorithms, and to instruct my engineering staff. This book is not only my main Verilog book, but it is my digital design reference as well.

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