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System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling

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Title: System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling
by Stuart Sutherland, Simon Davidmann, Peter Flake, Phil Moorby
ISBN: 1-4020-7530-8
Publisher: Kluwer Academic Publishers
Pub. Date: 01 January, 2004
Format: Hardcover
Volumes: 1
List Price(USD): $130.00
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Average Customer Rating: 2 (1 review)

Customer Reviews

Rating: 2
Summary: Good Overview but redundant
Comment: Here are my opinions after buying and reading the book.
- If you are student / fresher who wants to "learn" System Verilog then skip this book. This book assumes that you already know Verilog well.
- This book deals only with design. Authors plan to come up with one more for Verification.
- If you have plenty of cash ($130 for design and $130 for verification book) or your rich company pays for your books then go ahead and add this book to your library. If not then read free LRM http://www.eda.org/sv/SystemVerilog_3.1a.pdf
- Practice, practice, practice. Just by reading Verilog books no one has become a good design/verification engineer.

(...)Verilog won't become IEEE standard as it is. Thus this book will be superceded by a version which is slightly different anyway.

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